1. Field of the Invention
The present invention relates to a method for manufacturing a thin film transistor (TFT) panel.
2. Description of the Related Art
Unlike conventional monolithic transistors that are formed in the inside of a semiconductor substrate, thin-film transistors are fabricated by stacking several thin films on a substrate. Therefore, the thin-film transistors have a simple and easy-to-fabricate configuration compared with the monolithic transistors. As a result, the thin-film transistors have been in widespread use as, for example, switching elements in a large-sized electronic device such as an LCD device.
Further, the simplicity of the device configuration and fabrication method of the thin-film transistors makes it possible to fabricate various applied products at low cost, which contributes to popularization of them on the market.
In recent years, the above simplicity of the thin-film transistors has been further improved and progressed. Referring to FIG. 1, a thin-film transistor 10 includes a substrate 100, a semiconductor film 102, a source electrode 104, a drain electrode 106, a gate insulating film 108, and a gate electrode 110. The source and drain electrodes 104/106, which are located apart from each other on a same side of the semiconductor film 102, are electrically connected to the semiconductor film 102. The gate insulating film 108 is located on an opposite side of the semiconductor film 102 to the source electrode 104 and drain electrode 106. The gate electrode 110, which is located on the same side of the semiconductor film 102 as the gate insulating film 108, is opposite to the semiconductor film 102 through the gate insulating film 108. A conductive channel is formed in the gate-side surface region of the semiconductor film 102 under application of a proper gate voltage.
The semiconductor film 102 is typically formed by an undoped (or, i-type) semiconductor material. In this case, there is the need for interposing an n+ impurity semiconductor film 112 between the i-type semiconductor film 102 and the opposing source electrode 104 and drain electrode 106. The n+ impurity semiconductor film 112 is used to form source and drain contact regions between the undoped semiconductor film 102 and the source electrode 104 and drain electrode 106, respectively. The source and drain contact regions provide good ohmic contacts therebetween.
When the n+ impurity semiconductor film 102 serving as the source and drain contact regions is provided, the source electrode 104 and drain electrode 106 are short-circuited to each other by the n+ impurity doped semiconductor film 112 in a channel region 114, resulting in the so-called channel leakage. This channel leakage increases OFF current levels. Since low OFF current is required for display and imaging applications, this is a significant problem in devices of this kind. Therefore, it is necessary to add a back etching process to selectively remove the n+ impurity semiconductor film in the channel region 114 between the source and drain electrodes 104/106. Typically, the n+ semiconductor film 112 is etched by using Cl2/SF6 gases. However, the use of poisonous and corrosive material such as Cl2 should become obsolete in the next decade, because of the environmental concern in these years in the world. Furthermore, Cl2 is difficult to handle and is very poisonous and expensive.
The present invention therefore seeks to provide an improved method of manufacturing a TFT panel that overcomes, or at least reduces the above-mentioned problems of the prior art.
It is an object of the present invention to resolve the aforementioned channel leakage issue of the TFT panel by an insulating process without using any poisonous gas.
In the manufacturing method of a thin film transistor panel according to the present invention, a first metal pattern including at least a gate line with a gate electrode is formed on an insulating substrate such as a transparent glass substrate. Next, a gate insulating layer is deposited over the gate line. A semiconductor layer which comprises an amorphous silicon layer and an impurity-doped layer, e.g., an n+ amorphous silicon layer, is formed on the gate insulating layer. After the semiconductor layer is patterned, a conductive pattern layer is formed on the patterned semiconductor layer. The conductive pattern layer includes a source electrode, a drain electrode and a channel region disposed between the source electrode and the drain electrode. The impurity-doped layer has a portion located in the channel region and exposed through the conductive pattern layer.
Thereafter, the exposed portion of the impurity-doped layer in the channel region is insulated by a process, e.g., an oxidizing process, a nitridizing process or a p+ impurity doping process. The oxidizing process may be conducted by ultraviolet (UV) radiation, atmosphere plasma, O2 ashing or O3 treatment.
In the manufacturing method of a thin film transistor panel according to the present invention, the insulating step described above significantly reduces the conductivity of the exposed portion of the impurity doped layer. Therefore, the electrons in the impurity-doped layer between the source and drain electrodes can hardly be mobilized thereby overcoming or, at least, reducing the channel leakage problems. Furthermore, since no poisonous gas is involved in the aforementioned insulating step, the insulating step of the present invention can be achieved by a simple apparatus with low cost in comparison with the conventional back etching process using Cl2/SF6 gases.